Current Issue : July - September Volume : 2016 Issue Number : 3 Articles : 4 Articles
Hardware emulation of quantumsystems can mimicmore efficiently the parallel behaviour of quantumcomputations, thus allowing\nhigher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serialparallel\nhardware architecture targeted for field programmable gate array (FPGA) is proposed. Quantum Fourier transform and\nGrover�s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental\nwork shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline\nimplementations proposed in prior works.The proposed work contributes to the formulation of a proof-of-concept baseline FPGA\nemulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantumcircuits....
Moving target detection is the most common task for Unmanned Aerial Vehicle (UAV) to find and track object of interest from a\nbirdââ?¬â?¢s eye view in mobile aerial surveillance for civilian applications such as search and rescue operation. The complex detection\nalgorithm can be implemented in a real-time embedded system using Field Programmable Gate Array (FPGA). This paper presents\nthe development of real-time moving target detection System-on-Chip (SoC) using FPGA for deployment on a UAV.The detection\nalgorithm utilizes area-based image registration technique which includes motion estimation and object segmentation processes.\nThe moving target detection system has been prototyped on a low-cost Terasic DE2-115 board mounted with TRDB-D5M camera.\nThe system consists of Nios II processor and stream-oriented dedicated hardware accelerators running at 100MHz clock rate,\nachieving 30-frame per second processing speed for 640 Ã?â?? 480 pixelsââ?¬â?¢ resolution greyscale videos....
A set of soft IP cores for the Winograd ...
Popcount computations are widely used in such areas as combinatorial search, data processing, statistical analysis, and bio- and\nchemical informatics. In many practical problems the size of initial data is very large and increase in throughput is important.\nThe paper suggests two types of hardware accelerators that are (1) designed in FPGAs and (2) implemented in Zynq-7000\nall programmable systems-on-chip with partitioning of algorithms that use popcounts between software of ARM Cortex-A9\nprocessing system and advanced programmable logic. A three-level system architecture that includes a general-purpose computer,\nthe problem-specific ARM, and reconfigurable hardware is then proposed. The results of experiments and comparisons with\nexisting benchmarks demonstrate that although throughput of popcount computations is increased in FPGA-based designs\ninteracting with general-purpose computers, communication overheads (in experiments with PCI express) are significant and\nactual advantages can be gained if not only popcount but also other types of relevant computations are implemented in\nhardware. The comparison of software/hardware designs for Zynq-7000 all programmable systems-on-chip with pure software\nimplementations in the same Zynq-7000 devices demonstrates increase in performance by a factor ranging from 5 to 19 (taking\ninto account all the involved communication overheads between the programmable logic and the processing systems)....
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